8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) description the M62376GP is a semiconductor ic that adopts a cmos structure having 12-channel of 8-bit d-a converter and 12-bit i/o expander. the ic has achieved a wide operation range of 2.7v to 5.5v in power voltage. data is easily available via 3-wire combination system serial input of si, clk and en. the ic also provides an so pin enabling cascade connection. it provides 8 pins that share d-a converter and i/o ports that can be arbitrarily switched with serial input data. features supply voltage 2.7 to 5.5v adopts 4 special ports for each of dac and i/o and 8 ports that share dac output and i/o. each port can be set by serial data for input/output status. built-in power-on reset where d-a output is set to "l" in the initial status and i/o goes to hi-impedance when power is turned on. small package of 0.65mm pitch and 24 pin. application adjustment/control of industrial or home-use electronic equipment, such as vcr camera, vcr set, tv, and crt display. block diagram s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 decoder 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter shift register 21 22 19 20 23 13 14 24 v cc v dd gnd clk si so a12 a5 a4 a1 amp. hi-z 8-bit latch i/o select 12-bit latch output data 8-bit latch 12 15 18 5 d11/a5 d4/a12 d3 d0 1 a1 4 a4 output data 4-bit latch (12) clock control circuit en reset pin configuration (top view) outline 24p2e-a 24 21 22 23 1 4 3 2 20 5 19 6 18 7 17 8 16 9 15 10
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) explanation of terminals entry of low level into the en pin starts to read data. putting 16-bit data at high level after input loads the input data to a specified register. pin no. function symbol si 20 so 21 clk 19 22 a1 1 a2 2 a3 3 a4 4 d11/a5 5 d6/a10 10 d5/a11 11 d4/a12 12 d0 18 d1 17 d2 16 d3 15 v cc 14 gnd 24 d10/a6 6 d9/a7 7 d8/a8 8 d7/a9 9 serial data input pin. enters serial data of 16-bit in length. shift clock input pin. at the rise of shift clock, input signal from the si pin is entered into the 16-bit shift register. special output pin for 8-bit d-a converter (dac) digital block power supply pin. gnd pin outputs data from 16-bit shift register that reads serial data or parallel data. power supply pin in analog block and reference voltage input pin on the upper side of d-a converter pin that shares i/o and dac output. settings can be selected with serial data. d4 to d11 are connected to the v dd power supply. digital input output pin. reset pin v dd 13 23 en reset
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) explanation of terminals block diagram clock control power on reset en clk s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 di11 di10 di9 di8 di7 di6 di5 di4 di3 di2 di1 di0 decoder (12) decoder (4) level shift 8-bit latch 12-bit latch level shift [1111] [0000] level shift [11010000] (a5 to a12 hi-z) latch 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter 8-bit latch 8-bit d-a converter shift register 21 [1110] 22 19 20 23 1 12 15 16 17 18 4 5 clk si a1 a4 d11/a5 d4/a12 d3 d2 d1 d0 so (12) (8) (8) (4) (8) a12 a5 a4 a1 13 14 24 v dd v cc gnd [1101] level shift latch en reset en en
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) data structure serial data msb lsb s14 s15 s12 s13 s10 s11 s8 s9 s6 s7 s4 s5 s2 s3 s0 s1 data for dac and i/o expander address data i/o expander (serial parallel conversion) outputs data on s4 to s15 to pins d0 to d11. s3 s2 s1 s0 1 1 0 1 i/o expander (parallel serial conversion) writes data on d0 to d11 pins into s4 to s15. when next data communication is provided, outputs data sequentially from so pin at the rise of the shift clock (clk). s3 s2 s1 s0 1 1 1 0 i/o expander status setup register sets input/output pin of i/o expanders. data "0": input mode (hi-z status) "1": output mode s3 s2 s1 s0 1 1 1 1 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data pin x :don't care (*): only a5 to a12 outputs are available for dac output by s4 and hi-z conversion. dac data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s15 s14 s13 s12 s11 s10 0 0 0 1 1 0 s9 s8 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 x x x x x x x x analog output voltage (reference voltage on the lower side=0.0v fixed) x x x x x x s7 s6 x 0 x 0 x 0 s5 s4 x x x 0 x x x 0 x x x 1 (v dd /256)x1 [v] (1lsb) (v dd /256)x2 [v] (2lsb) (v dd /256)x3 [v] (3lsb) (v dd /256)x255 [v] (255lsb) v dd [v] (256lsb) high-impedance (i/o expander selected) (*) (a) command to set dac output to high-impedance (dachiz command) analog output voltage 0 s0 sets d-a output of a5 to a12 to high-impedance. 0 s1 0 s2 0 s3 1 s4 0 s5 1 s6 1 s7 x s8 x s9 x s10 x s11 x s12 x s13 x s14 x s15 address data s3 s2 s1 s0 setup 0 0 0 0 (a) 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 a1 selection a2 selection a4 selection a5 selection a3 selection a9 selection a11 selection a12 selection a10 selection a7 selection a8 selection a6 selection i/o expander (serial parallel conversion) i/o expander (parallel serial conversion) i/o expander status setup
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) (b) initial status just after power is turned on: low level output from a1 to a4 (set to [00]h) d4/a12 to d11/a5: dac output of high-impedance (hi-z), i/o of input mode (hi-z) d0 to d3 :input mode (hi-z) (c) the dachiz command is effective only for dac settings (a5 to a12), but not for the i/o ports (d0 to d11) note: to change the status of pins d4/a12 to d11/a5, switch both analog and digital after setup of high-impedance. symbol ratings unit parameter absolute maximum ratings v cc v digital supply voltage v dd v analog supply (d-a converter upper reference voltage) v in v input voltage v mw t opr ?c -20 to +85 operating temperature t stg ?c -40 to +125 storage temperature p d power dissipation conditions 200 v out output voltage -0.3 to 7.0 -0.3 to 7.0 -0.3 to v cc +0.3 v v in input voltage -0.3 to v dd +0.3 -0.3 to v cc +0.3 v v out output voltage -0.3 to v dd +0.3 v cc supply side pin v cc supply side pin v dd supply side pin v dd supply side pin timing chart (model) s0 s15 s0 s1 s2 s3 s12 s13 s14 s15 h-z n-1 n-1 n n n n n n n s12 s13 s14 s15 n-1 n-1 n-1 s0 s1 s2 s3 n-1 n-1 n-1 n-1 s15 n-2 h-z s15 n-2 s0 n-2 s15 n-3 h-z clk si parallel input ( serial output) (serial input ) parallel output so a1 to a12 d0 to d11 d0 to d11 en
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) digital part [v dd ] (v dd =2.7 to 5.5v, ta=-20 to +85 ? c, unless otherwise noted) limits min. typ. max. symbol test conditions unit v dd 5.5 supply voltage a 3.0 v il v -10 input low voltage v ih v input high voltage i ilk input leak current v 10 0.5v dd 2.7 v in =0 to v dd 0.2v dd v ol v output low voltage v oh v output high voltage v dd -0.4 i ol =2.5ma i oh =-400 a 0.4 note. for circuit current of v dd , see the analog block. parameter analog part (v dd (v refu ) =2.7 to 5.5v, ta=-20 to +85 ? c, unless otherwise noted) limits min. typ. max. symbol test conditions unit parameter ma i dd 1.5 3.5 dissipation current v v dd (v refu ) d-a converter upper reference voltage range 5.5 v ao v buffer amplifier output voltage range ma 0.2 2.7 i ao = 100 a +500 a -200 a v dd -0.1 i ao lsb buffer amplifier output drive range s dl lsb differential nonlinearity error v dd -0.2 s l lsb 2.0 nonlinearity error s zero f 2.0 zero code error r o buffer amplifier output impedance s full full scale error lsb 10 -2.0 -2.0 -1.5 -1.0 -0.3 1 1.5 v refu =3v input data condition: when maximum current of r-2r rudder is supplied v dd =2.700v (v refu ) without load (i ao =+0 a) c o output capacitative load w 1.0 in the setup range of reference voltage, all values are not taken with output. values to be taken depend on the item of buffer amplifier output voltage range. i ao = upper side saturation voltage=0.4v lower side saturation voltage=0.4v 0.1 5 symbol ratings unit parameter v cc v digital supply voltage v dd v analog supply (d-a converter upper reference voltage) v in v input pin voltage (v cc part) v conditions v out output pin voltage (v cc part) 2.7 to 5.5 2.7 to 5.5 0 to v cc v v in input pin voltage (v dd part) 0 to v dd 0 to v cc v v out output pin voltage (v dd part) 0 to v dd en, si, d0 to d3 so, d0 to d3 reset, d4/a12 to d11/a5 a1 to a4, d4/a12 to d11/a5 electrical characteristics recommended operating condition v dd 3 v cc digital part [v cc ] (v cc =2.7 to 5.5v, ta=-20 to +85 ? c, unless otherwise noted) limits min. typ. max. symbol test conditions unit v cc ma 5.5 supply voltage i cc a 3.0 2.5 supply current v il v -10 input low voltage v ih v input high voltage i ilk input leak current v 10 0.5v cc 2.7 clk=1mhz operation, v cc =3v, i ao =0 a v in =0 to v cc 0.2v cc v ol v output low voltage v oh v output high voltage v cc -0.4 v t+ v forward threshold voltage (en, clk) v t- v backward threshold voltage (en, clk) 0.2v cc 0.5v cc i ol =2.5ma i oh =-400 a 0.4 parameter
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) dut c l output input parameter ac electrical characteristics (v cc , v dd =2.7 to 5.5v, ta=-20 to +85?c, unless otherwise noted) limits min. typ. max. symbol test conditions unit t ckl clock low pulse width ? clock high pulse width 200 clock fall time data setup time clock rise time ns 200 200 c l =100pf data hold time clock (en) setup time en setup time t enh en high hold time t ckh t cr t cf t dch t chd t clh t chl t ldd t so t do serial data output delay time parallel data output delay time d-a output settling time c l =100pf c l 100pf, v ao :0.1 2.6v until output takes ?lsb of the final value. 350 600 100 200 30 60 100 200 ns ns ns ns ns ns ns ns ns clk si d0 to d11 input so output t clh t so t ckl t dch t cr t chd t ldd t do t dch t chd t enh t chl t cf t ckh d0 to d11 output a0 to a11 output timing chart en
8-bit 12ch d-a converter ic built-in 12-bit i/o expander M62376GP mitsubishi (dig./ana. interface) precaution for use this ic has two power supply pins and a ground pin. superimposition of these pins with ripple and spike noise may cause reduction of conversion accuracy and occurrence of malfunction. be sure to insert a capacitor between each power supply and the gnd pin to stabilize d-a converting operation. the output buffer amplifier of this ic has strong characteristics against capacitive load. accordingly, when the capacitance (10? max.) is connected between output and ground to remove jitter and noise due to installation of output line, no problem may occur in operation of dac. however, notice that the removal results in lengthening the settling time. this ic also provides power-on reset function. to assure the resetting operation, power supply should be turned on in the order of timing shown in the diagram below. (order): 1. v cc 2. v dd (*) the reset pin is directly connected with the power pin to use power-on reset. however, when forced reset is done from outside, the capacitance (0.1 to 10?) should be connected between reset pin and ground to remove noise due to installation of line, etc. v dd v cc time t
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